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general description the MAX1510/max17510 ddr linear regulators source and sink up to 3a peak (typ) using internal n-channel mosfets. these linear regulators deliver an accurate 0.5v to 1.5v output from a low-voltage power input (v in = 1.1v to 3.6v). the MAX1510/max17510 use a sepa- rate 3.3v bias supply to power the control circuitry and drive the internal n-channel mosfets. the MAX1510/max17510 provide current and thermal limits to prevent damage to the linear regulator. additionally, the MAX1510/max17510 generate a power-good (pgood) signal to indicate that the output is in regulation. during startup, pgood remains low until the output is in regulation for 2ms (typ). the internal soft-start limits the input surge current. the MAX1510/max17510 power the active-ddr termi- nation bus that requires a tracking input reference. the MAX1510/max17510 can also be used in low-power chipsets and graphics processor cores that require dynamically adjustable output voltages. the MAX1510/max17510 are available in a 10-pin, 3mm x 3mm thin dfn package. applications notebook/desktop computers ddr memory termination active termination buses graphics processor core supplies chipset/ram supplies as low as 0.5v features internal power mosfets with current limit (3a typ) fast load-transient response external reference input with reference output buffer 1.1v to 3.6v power input 15mv (max) load-regulation error thermal-fault protection shutdown input power-good window comparator with 2ms (typ) delay small, low-profile 10-pin, 3mm x 3mm tdfn package ceramic or polymer output capacitors MAX1510/max17510 low-voltage ddr linear regulators ________________________________________________________________ maxim integrated products 1 ordering information out in outs agnd pgnd v out = v tt v in (1.1v to 3.6v) v bias (2.7v to 3.6v) v ddq (2.5v or 1.8v) v refout = v ttr refout MAX1510 max17510 v cc pgood shdn refin typical operating circuit 19-3279; rev 5; 3/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin- package top mark MAX1510 etb -40 c to +85 c 10 tdfn-ep* ard MAX1510etb+ -40 c to +85 c 10 tdfn-ep* abd MAX1510atb/v+ -40 c to +85 c 10 tdfn-ep* awd max17510 atb+ - 40 c to + 125 c 10 tdfn-ep* awq max17510atb/v+ - 40 c to + 125 c 10 tdfn-ep* awq shdn outs pgood out pgnd agnd refin v cc tdfn 3mm x 3mm top view 5 1234 in refout MAX1510 max17510 a "+" sign will replace the first pin indicator on lead-free packages. + 6 10987 pin configuration + denotes a lead(pb)-free and rohs-compliant package. * ep = exposed pad. /v denotes an automotive qualified part.
MAX1510/max17510 low-voltage ddr linear regulators 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = 1.8v, v cc = 3.3v, v refin = v outs = 1.25v, shdn = v cc , circuit of figure 1, t j = t a = -40 c to +85 c for MAX1510etb, t j = t a = -40 c to +125 c for max17510atb, unless otherwise noted. typical values are at t a = +25 c.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in to pgnd............................................................-0.3v to +4.3v out to pgnd ..............................................-0.3v to (v in + 0.3v) outs to agnd ............................................-0.3v to (v in + 0.3v) v cc to agnd.........................................................-0.3v to +4.3v refin, refout, shdn , pgood to agnd ..-0.3v to (v cc + 0.3v) pgnd to agnd .....................................................-0.3v to +0.3v refout short circuit to agnd .................................continuous out continuous rms current: 100s .................................. 1.6a 1s......................................?.5a continuous power dissipation (t a = +70?) 10-pin 3mm x 3mm thin dfn (derated 24.4mw/ c above +70?)...........................1951mw operating temperature range MAX1510etb...................................................-40? to +85? max17510atb ..............................................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) lead(pb)-free packages..............................................+260? packages containing lead(pb).....................................+240? parameter symbol conditions min typ max units v in power input 1.1 3.6 input-voltage range v cc bias supply 2.7 3.6 v quiescent supply current (v cc )i cc load = 0, v refin > 0.45v 0.7 1.3 ma shdn = gnd, v refin > 0.45v 350 600 shutdown supply current (v cc )i cc ( shdn ) shdn = gnd, refin = gnd 50 100 ? quiescent supply current (v in )i in load = 0 0.4 10 ma shutdown supply current (v in )i in ( shdn ) shdn = gnd 0.1 10 ? t a = +25? -4 0 +4 feedback-voltage error v outs refin to outs i out = 200ma t a = -40? to +125? -6 +6 mv load-regulation error -1a i out +1a -15 +15 mv line-regulation error 1.4v v in 3.3v, i out = ?00ma 1 mv outs input-bias current i outs -1 +1 ? output output adjust range 0.5 1.5 v high-side mosfet (source) (i out = 0.1a) 0.14 0.25 out on-resistance low-side mosfet (sink) (i out = -0.1a) 0.14 0.25 ? output current slew rate c out = 100?, i out = 0.1a to 2a 3 a/? out power-supply rejection ratio psrr 10hz < f < 10khz, i out = 200ma, c out = 100? 80 db out-to-outs resistance r outs 12 k ? discharge mosfet on-resistance r discharge shdn = gnd 8 ?
MAX1510/max17510 low-voltage ddr linear regulators _______________________________________________________________________________________ 3 note 1: limits are 100% production tested at t a = +25 c. limits over the operating temperature range are guaranteed through cor- relation using statistical-quality-control (sqc) methods. electrical characteristics (continued) (v in = 1.8v, v cc = 3.3v, v refin = v outs = 1.25v, shdn = v cc , circuit of figure 1, t j = t a = -40 c to +85 c for MAX1510etb, t j = t a = -40 c to +125 c for max17510atb, unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units reference refin voltage range v refin 0.5 1.5 v refin input-bias current i refin t a = +25? -1 +1 a refin undervoltage-lockout voltage rising edge, hysteresis = 50mv 0.35 0.45 v refout voltage v refout v cc = 3.3v, i refout = 0v v refin - 0.01 v refin v refin + 0.01 v refout load regulation v refout i refout = 5ma -20 +20 mv fault detection thermal-shutdown threshold t shdn rising edge, hysteresis = 15? +165 ? v cc undervoltage-lockout threshold v uvlo rising edge, hysteresis = 100mv 2.45 2.55 2.65 v in undervoltage-lockout threshold rising edge, hysteresis = 55mv 0.9 1.1 v t a = -40? to +85? 1.8 3 4.2 current-limit threshold i limit t a = -40? to +125? 1.5 3 4.2 a soft-start current-limit time t ss 200 ? inputs and outputs pgood lower trip threshold with respect to feedback threshold, hysteresis = 12mv -200 -150 -100 mv pgood upper trip threshold with respect to feedback threshold, hysteresis = 12mv 100 150 200 mv pgood propagation delay t pgood outs forced 25mv beyond pgood trip threshold 51035s pgood startup delay startup rising edge, outs within 100mv of the feedback threshold 1 2 3.5 ms pgood output low voltage i sink = 4ma 0.3 v pgood leakage current i pgood outs = refin (pgood high impedance), pgood = v cc + 0.3v, t a = +25? 1a logic-high 2.0 v shdn logic input threshold logic-low 0.8 v shdn logic input current shdn = v cc or gnd, t a = +25? -1 +1 a
MAX1510/max17510 low-voltage ddr linear regulators 4 _______________________________________________________________________________________ 0.84 0.94 0.92 0.90 0.88 0.86 0.96 -3 3 -2 -1 0 1 2 output load regulation MAX1510/max17510 toc01 i out (a) v out (v) v refin = 0.9v v in = 1.2v v in = 1.5v 1.200 1.250 1.225 1.275 1.300 -3 3 -2 -1 0 1 2 output load regulation MAX1510/max17510 toc02 i out (a) v out (v) v refin = 1.25v v in = 1.5v v in = 1.8v 0 2.5 2.0 1.5 1.0 0.5 3.0 1.0 1.5 2.0 2.5 3.0 maximum output current vs. input voltage MAX1510/max17510 toc03 input voltage (v) maximum output current (a) dropout voltage limited thermally limited v out = 1.25v v out = 0.9v bias current (i cc ) vs. input voltage (v in ) MAX1510/max17510 toc05 v in (v) i cc (ma) 3.0 2.5 1.5 2.0 1.0 0.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 03.5 v out = 1.25v dropout input uvlo bias current (i cc ) vs. load current (i out ) MAX1510/max17510 toc06 i out (a) i cc (ma) 1 0 -1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 -2 2 v in = 1.5v v out = 1.25v v out = 0.90v entering dropout power ground current (i pgnd ) vs. source load current (i out ) MAX1510/max17510 toc07 i out (a) i pgnd (ma) 1.5 1.0 0.5 0.05 0.10 0.15 0.20 0.25 0 02.0 v out = 1.25v v out = 0.90v v in = 1.5v entering dropout input current (i in ) vs. sink load current (i out ) MAX1510/max17510 toc08 i out (a) i in (ma) -0.5 -1.0 -1.5 1 2 3 4 5 6 7 0 -2.0 0.0 v in = 1.5v v out = 0.90v v out = 1.25v 0 0.5 0.4 0.3 0.2 0.1 0.6 03.0 0.5 1.0 1.5 2.0 2.5 dropout voltage vs. output current MAX1510/max17510 toc09 output current (a) dropout voltage (v) v out = 1.25v v out = 0.9v typical operating characteristics (circuit of figure 1. t a = +25?, unless otherwise noted.) input current (i in ) vs. input voltage (v in ) MAX1510/max17510 toc04 v in (v) i in ( a) 3.0 2.5 2.0 1.5 1.0 0.5 50 100 150 200 250 0 03.5 v out = 1.25v v out = 0.90v
MAX1510/max17510 shutdown waveform MAX1510/max17510 toc12 100 s/div 5v 0v 0v 4v 2v 1v 0v v out pgood shdn r load = 100 source load transient MAX1510/max17510 toc13 20.0 s/div 1a 1mv/div 0a v out ac-coupled i out low-voltage ddr linear regulators _______________________________________________________________________________________ 5 source/sink load transient MAX1510/max17510 toc14 4.00 s/div +1.5a 5mv/div -1.5a v out ac-coupled i out line transient MAX1510/max17510 toc15 40 s/div 3.3v 0.9v 1.5v v in (1v/div) v out (10mv/div) ac-coupled i out = 100ma typical operating characteristics (continued) (circuit of figure 1. t a = +25?, unless otherwise noted.) -20 -15 -10 -5 0 5 10 15 20 -10 -5 0 5 10 refout voltage error vs. refout load current MAX1510/max17510 toc10 refout load current (ma) refout voltage error (mv) startup waveform MAX1510/max17510 toc11 500 s/div 5v 0v 0v 4v 0v 1.25v pgood v out shdn dynamic output-voltage transient MAX1510/max17510 toc16 20.0 s/div 2.5v 0.9v 0.9v 1.8v 1.2v 1.2v v refout v ddq v out v in = 1.5v
sink current-limit distribution t a = +125c MAX1510/max17510 toc20 sink current limit (a) sample percentage (%) 10 20 30 40 0 -4.00 -3.80 -3.60 -3.40 -3.20 -3.00 -2.80 -2.60 -2.40 -2.00 -2.20 50 sample size = 200 source current-limit distribution t a = +125c MAX1510/max17510 toc21 source current limit (a) sample percentage (%) 10 20 30 40 0 1.50 1.80 2.10 2.40 2.70 3.00 3.30 3.60 3.90 4.50 4.20 50 sample size = 200 sink load regulation distribution i out = -1a, t a = +125c MAX1510/max17510 toc22 sink load regulation (mv) sample percentage (%) 10 20 30 40 0 12 3456 7 8 9 11 10 50 sample size = 200 sink current-limit distribution t a = +125c MAX1510/max17510 toc20 sink current limit (a) sample percentage (%) 10 20 30 40 0 -4.00 -3.80 -3.60 -3.40 -3.20 -3.00 -2.80 -2.60 -2.40 -2.00 -2.20 50 sample size = 200 MAX1510/max17510 low-voltage ddr linear regulators 6 _______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1. t a = +25?, unless otherwise noted.) dynamic output-voltage transient MAX1510/max17510 toc17 20.0 s/div 2.5v 0.9v 0.9v 1.8v 1.2v 1.2v v refout v ddq v out v in = 1.8v sink current-limit distribution MAX1510/max17510 toc18 sink current limit (a) sample percentage (%) -2.5 -3.0 -3.5 10 20 30 40 50 0 -4.0 -2.0 sample size = 200 +25 c +85 c source current-limit distribution MAX1510/max17510 toc19 source current limit (a) sample percentage (%) 3.5 3.0 2.5 10 20 30 40 50 0 2.0 4.0 sample size = 200 +25 c +85 c
MAX1510/max17510 low-voltage ddr linear regulators _______________________________________________________________________________________ 7 detailed description the MAX1510/max17510 are low-voltage, low-dropout ddr termination linear regulators with an external bias supply input and a buffered reference output (see figures 1 and 2). v cc is powered by a 2.7v to 3.6v supply that is commonly available in laptop and desk- top computers. the 3.3v bias supply drives the gate of the internal pass transistor, while a lower voltage input at the drain of the transistor (in) is regulated to provide v out . by using separate bias and power inputs, the MAX1510/max17510 can drive an n-channel high-side mosfet and use a lower input voltage to provide bet- ter efficiency. the MAX1510/max17510 regulate their output voltage to the voltage at refin. when used in ddr applica- tions as a termination supply, the MAX1510/max17510 deliver 1.25v or 0.9v at 3a peak (typ) from an input voltage of 1.1v to 3.6v. the MAX1510/max17510 sink up to 3a peak (typ) as required in a termination sup- ply. the MAX1510/max17510 provide shoot-through protection, ensuring that the source and sink mosfets do not conduct at the same time, yet pro- duce a fast source-to-sink load transient. out in agnd pgnd v out = v tt = v ddq /2 c in2 10 f c out1 100 f c1 1.0 f r3 100k off v ddq on r2 10k 3.3v bias supply v in = 1.1v to 3.6v power-good r1 10k v refout = v ttr c refout 0.33 f refout MAX1510 max17510 v cc pgood shdn refin c refin 1000pf outs figure 1. standard application circuit pin name function 1 refout buffered reference output. the output of the unity-gain reference input buffer sources and sinks over 5ma. bypass refout to agnd with a 0.33? or greater ceramic capacitor. 2v cc analog supply input. connect to the system supply voltage (+3.3v). bypass v cc to agnd with a 1? or greater ceramic capacitor. 3 agnd analog ground. connect the backside pad to agnd. 4 refin external reference input. refin sets the output regulation voltage (v outs = v refin ). 5 pgood open-drain power-good output. pgood is low when the output voltage is more than 150mv (typ) above or below the regulation point, during soft-start, and when shut down. 2ms after the output reaches the regulation voltage during startup, pgood becomes high impedance. 6 outs output sense input. the outs regulation level is set by the voltage at refin. connect outs to the remote ddr termination bypass capacitors. outs is internally connected to out through a 12k resistor. 7 shdn shutdown control input. connect to v cc for normal operation. connect to analog ground to shut down the linear regulator. the reference buffer remains active in shutdown. 8 pgnd power ground. internally connected to the output sink mosfet. 9 out output of the linear regulator 10 in power input. internally connected to the output source mosfet. ?p exposed pad. internally connected to agnd. connect ep to agnd pcb ground plane to maximize thermal performance. not intended as an electrical connection point. pin description
MAX1510/max17510 low-voltage ddr linear regulators 8 _______________________________________________________________________________________ MAX1510 max17510 soft- start uvlo in input 1.1v to 3.6v out v tt 12k 8 pgnd outs en en gm agnd refout refin v cc 3.3v bias supply off on v ddq v ttr power- good shdn pgood refin +150mv refin -150mv thermal shdn delay logic figure 2. functional diagram
MAX1510/max17510 low-voltage ddr linear regulators _______________________________________________________________________________________ 9 the MAX1510/max17510 feature an open-drain pgood output that transitions high 2ms after the out- put initially reaches regulation. pgood goes low within 10? of when the output goes out of regulation by 150mv. the MAX1510/max17510 feature current- and thermal-limiting circuitry to prevent damage during fault conditions. 3.3v bias supply (v cc ) the v cc input powers the control circuitry and provides the gate drive to the pass transistor. this improves effi- ciency by allowing v in to be powered from a lower sup- ply voltage. power v cc from a well-regulated 3.3v supply. current drawn from the v cc supply remains rel- atively constant with variations in v in and load current. bypass v cc with a 1? or greater ceramic capacitor as close to the device as possible. v cc undervoltage lockout (uvlo) the v cc input undervoltage-lockout (uvlo) circuitry ensures that the regulator starts up with adequate volt- age for the gate-drive circuitry to bias the internal pass transistor. the uvlo threshold is 2.55v (typ). v cc must remain above this level for proper operation. power-supply input (in) in provides the source current for the linear regulator? output, out. in connects to the drain of the internal n- channel power mosfet. in can be as low as 1.1v, minimizing power dissipation. the input uvlo prohibits operation below 0.8v (typ). bypass in with a 10? or greater capacitor as close to the device as possible. reference input (refin) the MAX1510/max17510 regulate outs to the voltage set at refin, making the MAX1510/max17510 ideal for memory applications where the termination supply must track the supply voltage. typically, refin is set by an external resistive voltage-divider connected to the memory supply (v ddq ) as shown in figure 1. the maximum output voltage of 1.5v is limited by the gate-drive voltage of the internal n-channel power transistor. buffered reference output (refout) refout is a unity-gain transconductance amplifier that generates the ddr reference supply. it sources and sinks greater than 5ma. the reference buffer is typically connected to ceramic bypass capacitors (0.33? to 1.0?). refout is active when v refin > 0.45v and v cc is above v uvlo . refout is independent of shdn . shutdown drive shdn low to disable the error amplifier, gate- drive circuitry, and pass transistor (figure 2). in shut- down, out is terminated to gnd with an 8 mosfet. refout is independent of shdn . connect shdn to v cc for normal operation. current limit the MAX1510/max17510 feature source and sink cur- rent limits to protect the internal n-channel mosfets. the source and sink mosfets have a typical 3a cur- rent limit (1.8a min). this current limit prevents damage to the internal power transistors, but the device can enter thermal shutdown if the power dissipation increases the die temperature above +165 c (see the thermal-overload protection section). soft-start current limit soft-start gradually increases the internal source cur- rent limit to reduce input surge currents at startup. full- source current limit is available after the 200? soft-start timer has expired. the soft-start current limit is given by: where i limit and t ss are from the electrical characteristics. thermal-overload protection thermal-overload protection prevents the linear regula- tor from overheating. when the junction temperature exceeds +165?, the linear regulator and reference buffer are disabled, allowing the device to cool. normal operation resumes once the junction temperature cools by 15 c. continuous short-circuit conditions result in a pulsed output until the overload is removed. a continu- ous thermal-overload condition results in a pulsed out- put. for continuous operation, do not exceed the absolute maximum junction-temperature rating of +150?. i it t limit ss limit ss () =
power-good (pgood) the MAX1510/max17510 provide an open-drain pgood output that goes high 2ms (typ) after the out- put initially reaches regulation during startup as shown in figure 3. pgood transitions low 10? after the out- put goes out of regulation by 150mv, or when the device enters shutdown. connect a pullup resistor from pgood to v cc for a logic-level output. use a 100k resistor to minimize current consumption. applications information dynamic output-voltage transitions by changing the voltage at refin, the MAX1510/ max17510 can be used in applications that require dynamic output-voltage changes between two set points (graphics processors). figure 4 shows a dynam- ically adjustable resistive voltage-divider network at refin. using an external signal mosfet, a resistor can be switched in and out of the refin resistor- divider, changing the voltage at refin. the two output voltages are determined by the following equations: vv r rr vv rr rrr out low ref out high ref () () = + ? ? ? ? ? ? = + () ++ () ? ? ? ? ? ? ? ? 2 12 23 123 MAX1510/max17510 low-voltage ddr linear regulators 10 ______________________________________________________________________________________ MAX1510 max17510 refin r2 r1 c refin r3 reference voltage (v ref ) v out(high) (r2 + r3) r1 + (r2 + r3) v out(low) v out(high) = r2 r1 + r2 v out(low) = v ref v ref ( ) figure 4. dynamic output-voltage change figure 3. MAX1510/max17510 pgood and soft-start waveforms power-good window current limit out pgood 10 s propagation delay 2ms startup delay 10 s propagation delay 200 s output overload condition shdn
MAX1510/max17510 low-voltage ddr linear regulators ______________________________________________________________________________________ 11 for a step voltage change at refin, the rate of change of the output voltage is limited by the total output capacitance, the current limit, and the load during the transition. adding a capacitor across refin and agnd filters noise and controls the rate of change of the refin voltage during dynamic transitions. with the additional capacitance, the refin voltage slews between the two set points with a time constant given by r eq x c refin , where r eq is the equivalent parallel resistance seen by the slew capacitor. operating region and power dissipation the maximum power dissipation of the MAX1510/ max17510 depends on the thermal resistance of the 10- pin tdfn package and the circuit board, the tempera- ture difference between the die and ambient air, and the rate of airflow. the power dissipated in the device is: p src = i src x (v in ?v out ) p sink = i sink x v out the resulting maximum power dissipation is: where t j(max) is the maximum junction temperature (+150?), t a is the ambient temperature, jc is the ther- mal resistance from the die junction to the package case, and ca is the thermal resistance from the case through the pcb, copper traces, and other materials to the sur- rounding air. for optimum power dissipation, use a large ground plane with good thermal contact to the backside pad, and use wide input and output traces. when 1 square inch of copper is connected to the device, the maximum allowable power dissipation of a 10-pin dfn package is 1951mw. the maximum power dissipation is derated by 24.4mw/? above t a = +70?. extra copper on the pcb increases thermal mass and reduces thermal resistance of the board. refer to the MAX1510 evaluation kit for a layout example. the MAX1510/max17510 deliver up to 3a and oper- ates with input voltages up to 3.6v, but not simultane- ously. high output currents can only be achieved when the input-output differential voltages are low (figure 5). dropout operation a regulator? minimum input-to-output voltage differen- tial (dropout voltage) determines the lowest usable sup- ply voltage. because the MAX1510/max17510 use an n-channel pass transistor, the dropout voltage is a func- tion of the drain-to-source on-resistance (r ds(on) = 0.25 max) multiplied by the load current (see the typical operating characteristics ): v dropout = r ds(on) x i out for low output-voltage applications, the sink current is limited by the output voltage and the r ds(on) of the mosfet. input capacitor selection bypass in to pgnd with a 10? or greater ceramic capacitor. bypass v cc to agnd with a 1? ceramic capacitor for normal operation in most applications. typically, the ldo is powered from the output of a step-down controller (memory supply) that has addi- tional bulk capacitance (polymer or tantalum) and dis- tributed ceramic capacitors. output capacitor selection the MAX1510/max17510 output stability is indepen- dent of the output capacitance for c out from 10? to 220?. capacitor esr between 2m and 50m is needed to maintain stability. within the recommended capacitance and esr limits, the output capacitor should be chosen to provide good transient response: i out(p-p) x esr = v out(p-p) where i out(p-p) is the maximum peak-to-peak load- current step (typically equal to the maximum source load plus the maximum sink load), and v out(p-p) is the allowable peak-to-peak voltage tolerance. using larger output capacitance can improve efficiency in applications where the source and sink currents change rapidly. the capacitor acts as a reservoir for the rapid source and sink currents, so no extra current is supplied by the MAX1510/max17510 or discharged to ground, improving efficiency. p tt dis max j max a jc ca () () = + - ? 0 1.0 0.5 2.0 1.5 3.0 2.5 3.5 0 1.0 1.5 0.5 2.0 2.5 3.0 3.5 safe operating region input-output differential voltage (v) maximum output current (a) maximum current limit 100s rms limit 1s rms limit t a = +100 c t a = 0 c to +70 c dropout voltage limited v in(max) - v out(min) figure 5. power operating region?aximum output current vs. input-output differential voltage
MAX1510/max17510 low-voltage ddr linear regulators 12 ______________________________________________________________________________________ noise, psrr, and transient response the MAX1510/max17510 operate with low-dropout voltage and low quiescent current in notebook comput- ers while maintaining good noise, transient response, and ac rejection specifications. improved supply-noise rejection and transient response can be achieved by increasing the values of the input and output capaci- tors. use passive filtering techniques when operating from noisy sources. the MAX1510/max17510 load-transient response graphs (see the typical operating characteristics ) show two components of the output response: a dc shift from the output impedance due to the load-current change and the transient response. a typical transient response for a step change in the load current from -1.5a to +1.5a is 10mv. increasing the output capacitor? value and decreasing the esr attenuate the overshoot. pcb layout guidelines the MAX1510/max17510 require proper layout to achieve the intended output power level and low noise. proper layout involves the use of a ground plane, appropriate component placement, and correct routing of traces using appropriate trace widths. refer to the MAX1510 evaluation kit for a layout example: minimize high-current ground loops. connect the ground of the device, the input capacitor, and the output capacitor together at one point. to optimize performance, a ground plane is essen- tial. use all available copper layers in applications where the device is located on a multilayer board. connect the input filter capacitor less than 10mm from in. the connecting copper trace carries large currents and must be at least 2mm wide, preferably 5mm wide. connect the backside pad to a large ground plane. use as much copper as necessary to decrease the thermal resistance of the device. in general, more copper provides better heatsinking capabilities. chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 10 tdfn t1033+1 21-0137 90-0003
MAX1510/max17510 low-voltage ddr linear regulators maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 5/04 initial release 1 1/05 raised absolute maximum rating 1, 14 2 8/05 added MAX1510etb 1 3 4/09 added automotive-qualified part MAX1510etb/v+ 1, 2, 7, 12, 13 4 7/09 added max17510 to data sheet; added temperature grades for MAX1510atb+ and MAX1510atb/v+; minor edits 1, 2, 3, 6, 7, 12, 13 5 3/11 added max17510 automotive qualified part 1

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